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Dynamic voltage and frequency scaling: The laws of diminishing returns

Authors

Etienne Le Sueur and Gernot Heiser

UNSW

Abstract

Dynamic voltage and frequency scaling (DVFS) is a commonly-used power-management technique where the clock frequency of a processor is decreased to allow a corresponding reduction in the supply voltage. This reduces power consumption, which can lead to significant reduction in the energy required for a computation, particularly for memory-bound workloads.

However, recent developments in processor and memory technology have resulted in the saturation of processor clock frequencies, larger static power consumption, smaller dynamic power range and better idle/sleep modes. Each of these developments limit the potential energy savings resulting from DVFS. We analyse this trend by examining the potential of DVFS across three platforms with recent generations of AMD processors. We find that while DVFS is effective on the older platforms, it actually increases energy usage on the most recent platform, even for highly memory-bound workloads.

BibTeX Entry

  @inproceedings{LeSueur_Heiser_10,
    author           = {Le Sueur, Etienne and Heiser, Gernot},
    month            = oct,
    year             = {2010},
    keywords         = {power management, dvfs, operating systems},
    title            = {Dynamic Voltage and Frequency Scaling: The Laws of Diminishing Returns},
    booktitle        = {Workshop on Power Aware Computing and Systems},
    pages            = {1--5},
    address          = {Vancouver, Canada}
  }

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