Fast address-space switching on the StrongARM SA-1100 processor

Authors

Adam Wiggins and Gernot Heiser

    School of Computer Science and Engineering
    UNSW,
    Sydney 2052, Australia

Abstract

The StrongARM SA-1100 is a high-speed low-power processor aimed at embedded and portable applications. Its architecture features virtual caches and TLBs which are not tagged by an address-space identifier. Consequently, context switches on that processor are potentially very expensive, as they may require complete flushes of TLBs and caches.

This report presents the design of an address-space management technique for the StrongARM which minimises TLB and cache flushes and thus context switching costs. The basic idea is to implement the top-level of the (hardware-walked) page-table as a cache for page directory entries for different address spaces. This allows switching address spaces with minimal overhead as long as the working sets do not overlap. For small (<=32MB) address spaces further improvements are possible by making use of the StrongARM's re-mapping facility. Our technique is discussed in the context of the L4 microkernel in which it will be implemented.

BibTeX Entry

  @inproceedings{Wiggins_Heiser_00,
    publisher        = {IEEE Computer Society Press},
    author           = {Adam Wiggins and Gernot Heiser},
    title            = {Fast Address-Space Switching on the {StrongARM} {SA-1100} Processor},
    booktitle        = {Proceedings of the 5th Australasian Computer Architecture Conference},
    month            = {jan},
    year             = {2000},
    pages            = {97--104},
    address          = {Canberra, Australia}
  }

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